Building a custom RISC-V based SoC on an FPGA

A two-part series describing development of a SoC based on PicoRV32 RISC-V core, and a set of commonly used peripherals: SRAM, Bootrom, Timers/Counters, UART, and a simple GPIO. Part 1 mostly focuses on the architectural decisions, hardware design and hardware verification. Part 2 describes backend work (Synthesis, Place and Route, Bitstream Generation) and software development.

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